1. Field of the Invention
The present invention relates to input offset compensation in a DC (Direct Current) feedback differential amplification circuit.
2. Description of the Related Art
Conventionally, a DC feedback circuit used to stabilize a DC component of an input voltage is utilized with a single input.
FIG. 1 exemplifies the configuration of a single-input differential amplification feedback circuit.
A DC component is removed by an operation of a capacitor 60 from a signal from an input terminal 68, and only an AC (Alternating Current) component is extracted. A DC component generated by a voltage drop caused by resistors 61 and 62 is added to the signal which includes only the AC component, and the resultant signal is input to one of input terminals of a differential amplifier 63. A normal signal obtained by amplifying the above described signal and its inverted signal are output from a differential amplifier 63. Here, a feedback path is formed in order to stabilize the DC components. That is, in the configuration shown in FIG. 1, the normal output and the inverted output of the differential amplifier 63 are input to a low-pass filter 64. After their DC components are extracted, these signals are input to a differential amplifier 65. The differential amplifier 65 amplifies and outputs a difference between the DC component of the normal output of the differential amplifier 63 and that of the inverted output, and inputs the difference to the other of the input terminals of the differential amplifier 63. By arranging the path for feeding back only the DC component, the DC components of the signals output from output terminals 66 and 67 are stabilized and output.
However, in the above described single-input amplification circuit, unless the gain of the differential amplifier 63 are sufficiently increased for a predetermined input voltage from the input terminal 68, it is insufficient for amplifying, for example, a signal which is much attenuated within an SAW filter and output therefrom. Accordingly, a normal signal and its inverted signal are considered to be input to the differential amplifier 63. In this way, the amplitude of a signal can be substantially doubled, and at the same time, an S/N ratio can be improved on the condition that the level of noise is approximate to that in the case of a single input.
FIGS. 2A and 2B exemplify the configurations of a conventional DC feedback differential amplification circuit when a differential input is made.
Considered as the DC feedback configuration for compensating for the offset between DC components when the differential input is made is a configuration in which a low-pass filter 80 having a high-frequency cut-off frequency "fc1" in order to feed back a DC component to the input is added as shown in FIG. 2A or 2B.
In FIG. 2A, a normal signal of a signal to be input is input from an input terminal 71, while an inverted signal of the signal to be input is input from an input terminal 72. A DC component is removed by a capacitor 73 from the signal from the input terminal 71. The DC component set by resistors 75 and 76 is newly added to this signal, which is input to one of terminals of a differential amplifier 79. A DC component is removed by a capacitor 74 also from the inverted signal from the input terminal 72, and a DC component set by the resistors 77 and 78 is newly added. This signal then is input to the other of the terminals of the differential amplifier 79. The differential amplifier 79 outputs to an output terminal 82 a normal signal obtained by amplifying the difference between the inputs from the two terminals, and outputs the inverted signal of the amplified signal to an output terminal 83. The signals to be output to the output terminals 82 and 83 are input to a low-pass filter 80 via feedback paths. The low-pass filter extracts DC components, and the signals are input to a differential amplifier 81. The differential amplifier amplifies the difference between the two DC voltage, and feeds back the amplified difference to the input side of the inverted signal of the differential amplifier 79. In such a configuration, if there is a difference between the DC components of the signals to be fed to the output terminals 82 and 83, the difference is amplified by the differential amplifier 81 and again input to the differential amplifier 79. As a result, the DC components of the signals to be fed to the output terminals 82 and 83 can be matched, thereby compensating for the offset between the DC components.
FIG. 2B shows a modification of the configuration shown in FIG. 2A.
In the configuration shown in FIG. 2A, the positions at which the low-pass filter 80 and the differential amplifier 81 on the feedback paths are arranged are reversed from those shown in FIG. 2A. However, their operations are the same as those of the configuration shown in FIG. 2A.
That is, the signal input from the input terminal 72 is an inversion of the signal from the input terminal 71. DC components are removed from the signals by the capacitors 73 and 74 from the signals from the input terminals 71 and 72. The respective DC components set by the resistors 75 and 76, and 77 and 78 are newly added, and the signals are input to the differential amplifier 79. The normal and the inverted outputs of the differential amplifier 79 are fed to the differential amplifier 81 via feedback paths, and the difference between the normal and the inverted outputs is amplified, and the amplified difference is input to the low-pass filter 80. The low-pass filter 80 extracts only a DC component, and feeds back the extracted component to the differential amplifier 79. Also in this case, if the DC components of the outputs of the output terminals 82 and 83 are large, a corresponding DC voltage is input from the low-pass filter 80 to the differential amplifier 79, so that the difference between the DC components of the normal and the inverted outputs of the differential amplifier 79, is eliminated. Since the offset between the DC components is cancelled and output as described above, the normal and the inverted signals whose DC component values are matched are output.
In the conventional circuitry shown in FIG. 2A or 2B, a high-frequency cut-off frequency "fc1" of the low-pass filter arranged for removing only a high frequency component and feeding back only a DC component exists within a DC feedback loop. In addition, a high-frequency cut-off frequency "fc2" is caused within a DC feedback loop by the output impedance of the capacitor 74 which is intended to remove a DC component of an input signal and to input only a high frequency component, and the differential amplifier 81. The high-frequency cut-off frequency "fc1" must be sufficiently low for the frequency of the signal so as to perform a DC feedback operation. Also the high-frequency cut-off frequency "fc2" must be low so as to increase the value of the capacitor 74 in consideration of the same code succession of the signal. Furthermore, the gain of the DC feedback loop must be increased so as to reduce the compression residual of the offset. In this case, a sufficient phase margin cannot be secured for the gain of the feedback loop, which leads to oscillation of the feedback loop.
FIG. 3 explains a phase margin in the circuitry shown in FIGS. 2A and 2B.
As shown in the upper stage, the loop gain decreases as the frequency increases. Especially, the loop gain significantly decreases at the high-frequency cut-off frequencies "fc1" and "fc2". The loop gain becomes smaller than 0 dB at a certain frequency. The phase of the loop gain starts to rotate at the high-frequency cut-off frequencies "fc1" and "fc2". At the high-frequency cut-off frequency "fc1", the phase shifts from 180.degree. to 90.degree.. When the phase exceeds the high-frequency cut-off frequency "fc2", the phase starts to decrease from 90.degree. and finally reaches 0.degree.. For the feedback loop, the phase of the feedback loop itself starts to oscillate if it is close to 0.degree. at the frequency where the loop gain reaches 0 dB, which leads to a circuit malfunction. The phase of the loop gain at the frequency where the loop gain becomes 0 dB is referred to as a phase margin. Normally, the phase margin required to suppress oscillation is 45.degree.. However, a phase margin of 45.degree. or more cannot be secured in the circuitry shown in FIGS. 2A and 2B, which causes oscillation. Accordingly, measures must be taken to decrease the absolute value of the loop gain in such circuitry. At the same time, however, a contradictory demand for increasing the loop gain must be satisfied in order to improve the offset compensation effect of the circuity.